1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to an improvement of a cache DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
FIG. 20 is a concept diagram showing a structure of a conventional cache DRAM. Referring to FIG. 20, a cache DRAM 1900 includes a main memory 101 storing a large amount of data required for an MPU (Main Processing Unit), and a cache memory 103 storing a part of the data. Generally, a DRAM is used for main memory 101, and an SRAM (Static Random Access Memory) is used for cache memory 103. These memories 101 and 103 are formed on one chip.
The MPU is connected to main memory 101 through cache memory 103. Almost all data required for the MPU is stored in main memory 101. Out of the data, data which is accessed at a high frequency is stored in cache memory 103, thereby preventing the operation speed of the MPU from being determined by an access time to main memory 101. More specifically, since the access speed of the DRAM configuring main memory 101 is lower than the operation speed of the MPU, if the MPU directly accesses main memory 101, the MPU must wait for reading or writing of the DRAM to complete during several cycles. On the other hand, the access speed of the SRAM configuring cache memory 103 is higher than that of the DRAM. Therefore, since data which is accessed at a high frequency is stored in cache memory 103 in this cache DRAM, substantial reduction of the operation speed of the MPU is prevented.
FIG. 21 is a block diagram showing a specific structure of the cache DRAM of FIG. 20. Referring to FIG. 21, cache DRAM 1900 includes main memory 101, cache memory 103, a data buffer 203 for inputting/outputting data Din/Dout, a CS buffer 205 for receiving a chip select signal CS, an address buffer 201 for receiving an address signal Add, a tag memory 207 for storing an address in the main memory of data stored in cache memory 103, a synchronous arbiter 115 for controlling access to main memory 101, a refresh controller 211 for controlling refresh of main memory 101, and a clock generating circuit 213 for generating a clock signal for controlling refresh controller 211.
Data which is accessed at a high frequency out of the data stored in main memory 101 is also stored in cache memory 103. The address in main memory 101 of the data stored in cache memory 103 is stored in tag memory 207. Tag memory 207 is also called a content addressable memory (CAM). Data buffer 203 serves as an interface for cache memory 103. In response to chip select signal CS, data buffer 203, address buffer 201, cache memory 103, and tag memory 207 are activated. When an externally supplied address matches the address stored in tag memory 207, data in cache memory 103 is accessed. Such a case is called a hit. On the other hand, when an externally supplied address does not match the address stored in tag memory 207, data in main memory 101 is accessed. This case is called a miss.
Since the storage capacity of cache memory 103 is limited, data whose access frequency is decreased must be transferred to main memory 101. In this case, the data is transferred to main memory 101 according to the address corresponding to the data stored in tag memory 207. Simultaneously with such data transfer from cache memory 103 to main memory 101, an address for refreshing main memory 101 is sometimes transferred from refresh controller 211. Synchronous arbiter 115 is provided for avoiding such a contention of access to main memory 101. While main memory 101 is refreshed, data transfer from cache memory 103 or data buffer 203 to main memory 101, or data transfer from main memory 101 to cache memory 103 or data buffer 203 is suppressed. When refresh is completed, the above described data transfer is started.
As described above, the transfer operation between units such as main memory 101, cache memory 103, and refresh controller 211 is carried out synchronously in response to an externally supplied clock signal. Therefore, while refresh controller 211 refreshes main memory 101, cache memory 103 must refrain data transfer to main memory 101. Since the MPU cannot access cache memory 103 during this period, the operation speed of the MPU is restricted.